<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>ISA on wiredwisdom</title><link>https://wiredwisdom.netlify.app/tags/isa/</link><description>Recent content in ISA on wiredwisdom</description><generator>Hugo -- gohugo.io</generator><language>en</language><copyright>© 2026</copyright><lastBuildDate>Wed, 25 Feb 2026 00:00:00 +0000</lastBuildDate><atom:link href="https://wiredwisdom.netlify.app/tags/isa/index.xml" rel="self" type="application/rss+xml"/><item><title>[SoC-04] Instruction Set Architecture Part 1: The CPU's Contract with Software</title><link>https://wiredwisdom.netlify.app/posts/soc-04-isa-part1/</link><pubDate>Wed, 25 Feb 2026 00:00:00 +0000</pubDate><guid>https://wiredwisdom.netlify.app/posts/soc-04-isa-part1/</guid><description/></item><item><title>[SoC-05] Instruction Set Architecture Part 2: Addressing, CISC vs RISC, and the RISC-V Philosophy</title><link>https://wiredwisdom.netlify.app/posts/soc-05-isa-part2/</link><pubDate>Wed, 25 Feb 2026 00:00:00 +0000</pubDate><guid>https://wiredwisdom.netlify.app/posts/soc-05-isa-part2/</guid><description/></item><item><title>[SoC-06] Instruction Set Architecture Part 3: RISC-V in Action — From C to Machine Code</title><link>https://wiredwisdom.netlify.app/posts/soc-06-isa-part3/</link><pubDate>Wed, 25 Feb 2026 00:00:00 +0000</pubDate><guid>https://wiredwisdom.netlify.app/posts/soc-06-isa-part3/</guid><description/></item><item><title>RISC-V R-Type Instructions</title><link>https://wiredwisdom.netlify.app/posts/riscv-r-type/</link><pubDate>Tue, 25 Jun 2024 00:00:00 +0000</pubDate><guid>https://wiredwisdom.netlify.app/posts/riscv-r-type/</guid><description/></item></channel></rss>