<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Digital Logic on wiredwisdom</title><link>https://wiredwisdom.netlify.app/tags/digital-logic/</link><description>Recent content in Digital Logic on wiredwisdom</description><generator>Hugo -- gohugo.io</generator><language>en</language><copyright>© 2026</copyright><lastBuildDate>Wed, 25 Feb 2026 00:00:00 +0000</lastBuildDate><atom:link href="https://wiredwisdom.netlify.app/tags/digital-logic/index.xml" rel="self" type="application/rss+xml"/><item><title>[SoC-02] Digital System Basics: The Foundation of Every Computer</title><link>https://wiredwisdom.netlify.app/posts/soc-02-digital-system-basics/</link><pubDate>Wed, 25 Feb 2026 00:00:00 +0000</pubDate><guid>https://wiredwisdom.netlify.app/posts/soc-02-digital-system-basics/</guid><description/></item><item><title>Latches and Flip-Flops: The Fundamentals of Digital Memory</title><link>https://wiredwisdom.netlify.app/posts/latch-flipflop-basics/</link><pubDate>Thu, 19 Feb 2026 00:00:00 +0000</pubDate><guid>https://wiredwisdom.netlify.app/posts/latch-flipflop-basics/</guid><description/></item><item><title>RTL Design: A Practical Introduction to Register-Transfer Level</title><link>https://wiredwisdom.netlify.app/posts/rtl-introduction/</link><pubDate>Thu, 19 Feb 2026 00:00:00 +0000</pubDate><guid>https://wiredwisdom.netlify.app/posts/rtl-introduction/</guid><description/></item></channel></rss>