[SoC-04] Instruction Set Architecture Part 1: The CPU's Contract with Software

Introduction

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In the previous posts, we covered digital logic fundamentals and computer arithmetic. Now we arrive at one of the most important concepts in computer architecture:

What exactly can a CPU do?

The answer is defined by the Instruction Set Architecture (ISA) — the complete specification of every instruction the processor understands. Think of it as a contract between software and hardware:

• Software (compilers, operating systems, applications) promises to express all computation using only the instructions defined in the ISA.
• Hardware (the processor) promises to execute every instruction correctly and predictably.

This separation is powerful because it allows software and hardware to evolve independently, as long as both sides honor the contract.

1. What Is an ISA?

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1.1 Definition

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An Instruction Set Architecture specifies:

1. Instructions: The operations the CPU can perform (add, subtract, load, store, branch, etc.)
2. Data types: What kinds of data the CPU can operate on (integers, floating-point, vectors)
3. Registers: How many registers are available and their purpose
4. Memory model: How the CPU accesses memory (addressing modes, alignment, endianness)
5. Encoding: How instructions are represented as binary bit patterns

1.2 The ISA as an Abstraction Layer

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┌─────────────────────────┐
│     Application          │  (Python, Java, C++)
├─────────────────────────┤
│     Operating System     │  (Linux, Windows, RTOS)
├─────────────────────────┤
│     Compiler             │  (GCC, LLVM, Clang)
├═════════════════════════╡
│     ISA                  │  ◄── THE CONTRACT
├═════════════════════════╡
│     Microarchitecture    │  (Pipeline, Cache, OoO)
├─────────────────────────┤
│     Logic / RTL          │  (Gates, Flip-flops)
├─────────────────────────┤
│     Physics / Silicon    │  (Transistors, Metal layers)
└─────────────────────────┘

Everything above the ISA is software. Everything below is hardware implementation. The ISA is the boundary.

Key insight: Multiple different microarchitectures can implement the same ISA. For example:

• Intel’s Alder Lake and AMD’s Zen 4 both implement the x86-64 ISA, but with completely different internal designs
• ARM’s Cortex-A78 and Cortex-A55 both implement ARMv8-A, but one is high-performance while the other is energy-efficient

1.3 Why ISA Matters for SoC Design

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When designing an SoC, the choice of ISA determines:

2. Anatomy of an Instruction

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Every instruction tells the CPU three things:

1. What to do (the operation) → encoded in the opcode
2. What to do it to (the data) → specified by operands
3. Where to put the result → specified by the destination operand

2.1 A Simple Example

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Consider this high-level operation:

c = a + b;

In assembly (RISC-V):

add  x3, x1, x2    # x3 = x1 + x2

The instruction has four fields:

2.2 Instruction Fields

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In general, instructions contain these types of fields:

┌──────────┬──────────┬──────────┬──────────┬──────────┐
│  Opcode  │   Dest   │  Source1 │  Source2 │  Other   │
│  (what)  │ (where)  │  (from)  │  (from)  │ (extra)  │
└──────────┴──────────┴──────────┴──────────┴──────────┘

3. Types of Instructions

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A typical ISA provides four main categories of instructions:

3.1 Arithmetic and Logic Instructions

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Perform computation on register values:

With immediate values (constant operands):

3.2 Memory Access Instructions (Load/Store)

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Transfer data between registers and memory:

   Registers                    Memory
  ┌────────┐                 ┌────────────┐
  │   x1   │ ──── Store ──► │ Address A  │
  │   x2   │ ◄─── Load ──── │ Address B  │
  │   ...  │                 │    ...     │
  └────────┘                 └────────────┘

The syntax offset(base) means: compute the memory address as base register + offset.

3.3 Control Flow Instructions (Branch/Jump)

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Change the order of instruction execution:

Conditional branches (decide based on comparison):

Unconditional jumps:

jal is used for function calls — it saves the return address in the destination register before jumping.

3.4 System Instructions

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Special operations for OS interaction and hardware control:

4. Instruction Encoding

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4.1 Why Encoding Matters

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Every instruction must be stored in memory as a sequence of bits. The encoding format determines:

• How the CPU decodes (interprets) instructions
• How much memory instructions consume
• How complex the decoder hardware needs to be

4.2 Fixed-Length vs. Variable-Length

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RISC-V uses fixed 32-bit instructions (with an optional 16-bit compressed extension). This means every instruction is exactly 4 bytes, which makes the hardware decoder much simpler.

4.3 RISC-V Base Instruction Formats

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RISC-V defines six instruction formats, all exactly 32 bits wide:

R-type:  [  funct7  |  rs2  |  rs1  | funct3 |   rd   | opcode ]
         [  31:25   | 24:20 | 19:15 | 14:12  |  11:7  |  6:0   ]

I-type:  [     imm[11:0]    |  rs1  | funct3 |   rd   | opcode ]
         [      31:20       | 19:15 | 14:12  |  11:7  |  6:0   ]

S-type:  [ imm[11:5] |  rs2  |  rs1  | funct3 |imm[4:0]| opcode ]
         [  31:25    | 24:20 | 19:15 | 14:12  |  11:7  |  6:0   ]

B-type:  [imm[12|10:5]| rs2  |  rs1  | funct3 |imm[4:1|11]|opcode]
         [   31:25    | 24:20| 19:15 | 14:12  |  11:7  |  6:0   ]

U-type:  [          imm[31:12]          |   rd   | opcode ]
         [            31:12             |  11:7  |  6:0   ]

J-type:  [  imm[20|10:1|11|19:12]       |   rd   | opcode ]
         [            31:12             |  11:7  |  6:0   ]

Design principle: Notice that rs1, rs2, and rd are always in the same bit positions across all formats. This allows the register file to be read before the instruction is fully decoded — a critical optimization for pipelined processors.

4.4 Format Usage

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5. Registers

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5.1 Why Registers?

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Registers are the fastest storage in a computer — they are built directly into the CPU and can be accessed in a single clock cycle (or even less). Memory access, by contrast, takes many cycles.

Speed Hierarchy:
  Registers    ──→  ~0.5 ns   (within CPU)
  L1 Cache     ──→  ~1–2 ns
  L2 Cache     ──→  ~5–10 ns
  Main Memory  ──→  ~50–100 ns  (100× slower than registers!)
  SSD          ──→  ~100 μs

5.2 RISC-V Register File

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RISC-V has 32 general-purpose registers, each 32 bits wide (in RV32I) or 64 bits (in RV64I):

Why is x0 hardwired to 0? It simplifies many operations:

• add x3, x1, x0 → move (copy x1 to x3)
• addi x0, x0, 0 → nop (no operation)
• slt x3, x0, x1 → test if x1 > 0

5.3 Register Design Trade-offs

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RISC-V’s choice of 32 registers is a well-established sweet spot — enough to keep most operands in registers, but not so many that instruction encoding becomes bloated (5 bits per register specifier × 3 registers = 15 bits, leaving room for opcode and immediates in 32-bit instructions).

6. The Program Counter (PC)

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6.1 What Is the PC?

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The Program Counter is a special register that holds the memory address of the current instruction being executed. After each instruction, the PC is typically updated to point to the next instruction:

Unless a branch or jump instruction redirects execution elsewhere.

6.2 Program Execution Flow

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Memory:
┌──────────┬──────────────────┐
│ Address  │ Instruction      │
├──────────┼──────────────────┤
│ 0x0000   │ addi x1, x0, 5  │ ◄── PC starts here
│ 0x0004   │ addi x2, x0, 3  │
│ 0x0008   │ add  x3, x1, x2 │
│ 0x000C   │ sw   x3, 0(x4)  │
│ 0x0010   │ beq  x3, x5, L  │ ── Branch: if taken, PC jumps to L
│ 0x0014   │ addi x1, x1, 1  │
│ 0x0018   │ ...              │ ◄── L (branch target)
└──────────┴──────────────────┘

The CPU repeats this cycle endlessly:

┌────────────────────────────────┐
│   1. FETCH instruction at PC   │
│   2. DECODE the instruction    │
│   3. EXECUTE the operation     │
│   4. UPDATE the PC             │
│              │                 │
│              ▼                 │
│       (repeat forever)         │
└────────────────────────────────┘

This is the fetch-decode-execute cycle — the fundamental heartbeat of every processor.

7. Operand Types

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Instructions can get their data from three sources:

7.1 Register Operands

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Data comes from the register file. This is the fastest option.

add  x3, x1, x2   # All operands are registers

7.2 Immediate Operands

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A constant value is encoded directly in the instruction bits. No memory or register lookup needed.

addi x3, x1, 42   # 42 is the immediate value

Immediates have limited range because they must fit within the instruction:

• I-type: 12 bits → range $[-2048, +2047]$
• U-type: 20 bits → for loading upper bits of large constants

Loading a full 32-bit constant requires two instructions:

lui  x3, 0x12345    # Load upper 20 bits: x3 = 0x12345000
addi x3, x3, 0x678  # Add lower 12 bits:  x3 = 0x12345678

7.3 Memory Operands

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Data is loaded from or stored to memory at a computed address:

lw  x3, 8(x1)     # x3 = Memory[x1 + 8]
sw  x3, 8(x1)     # Memory[x1 + 8] = x3

In RISC architectures like RISC-V, only load and store instructions access memory. All computation happens on registers. This is called a load-store architecture.

8. Instruction Execution: Putting It All Together

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Let’s trace through a complete example — computing a[3] = a[1] + a[2]:

Given: base address of array a is in x10, each element is 4 bytes (word).

# Step 1: Load a[1] into x5
lw   x5, 4(x10)     # x5 = Memory[x10 + 4] = a[1]

# Step 2: Load a[2] into x6
lw   x6, 8(x10)     # x6 = Memory[x10 + 8] = a[2]

# Step 3: Add them
add  x7, x5, x6     # x7 = x5 + x6 = a[1] + a[2]

# Step 4: Store result into a[3]
sw   x7, 12(x10)    # Memory[x10 + 12] = x7 → a[3] = a[1] + a[2]

Execution trace:

Step  PC      Instruction         Registers Changed
────  ──────  ──────────────────  ─────────────────────
  1   0x0000  lw  x5, 4(x10)     x5 ← Memory[x10+4]
  2   0x0004  lw  x6, 8(x10)     x6 ← Memory[x10+8]
  3   0x0008  add x7, x5, x6     x7 ← x5 + x6
  4   0x000C  sw  x7, 12(x10)    Memory[x10+12] ← x7

9. Design Principles Behind ISA

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Several guiding principles shape good ISA design:

Principle 1: Simplicity Favors Regularity

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All RISC-V arithmetic instructions have the same format: op rd, rs1, rs2. This regularity makes the hardware decoder simple and fast.

Principle 2: Smaller Is Faster

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RISC-V has 32 registers — not 64 or 128. A smaller register file is faster to access, consumes less power, and requires fewer bits in each instruction to specify.

Principle 3: Good Design Demands Compromise

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The ISA must balance competing goals:

• Large immediates (more flexibility) vs. short instructions (less memory)
• Many instruction types (more expressiveness) vs. simple decoder (less hardware)

Principle 4: Make the Common Case Fast

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The most frequently used instructions should be the simplest and fastest. RISC-V’s base integer ISA (RV32I) contains only 47 instructions — just enough for a complete computer, but no more.

10. Summary

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In the next post ([SoC-05]), we will dive deeper into memory addressing modes, compare CISC vs. RISC architectures, and explore the design philosophy of RISC-V.

This post is part of the SoC Design Course series. Navigate to the next post to continue your learning journey.