Table of Contents
Overview#
The “Power Wall” refers to the practical limit on processor power consumption, which has fundamentally changed CPU design strategy since the mid-2000s.
The Problem#
Dennard Scaling (Historical)#
In the past, as transistors shrunk:
- Voltage decreased proportionally
- Power density remained constant
- Clock speeds could increase
Dennard Scaling Breakdown (~2005)#
Below ~65nm process:
- Voltage can’t decrease further (leakage)
- Power density increases with shrinking
- Heat dissipation becomes impossible
Power Equation#
Dynamic Power#
$$ P_{dynamic} = \alpha \cdot C \cdot V^2 \cdot f $$Where:
- \(\alpha\): Activity factor
- \(C\): Capacitance
- \(V\): Voltage
- \(f\): Frequency
Static Power (Leakage)#
$$ P_{static} = I_{leak} \cdot V $$Increases exponentially with smaller transistors.
Total Power#
$$ P_{total} = P_{dynamic} + P_{static} $$Why We Hit the Wall#
Heat Dissipation Limits#
| Device | Typical TDP |
|---|---|
| Desktop CPU | 65-125W |
| Laptop CPU | 15-45W |
| Mobile SoC | 5-10W |
| Air cooling limit | ~100W/cm² |
Clock Frequency Stagnation#
Year Max Clock (GHz)
2002 3.0
2004 3.4
2006 3.6
2010 3.8
2015 4.0
2020 5.0
2024 6.0 (extreme)Growth dramatically slowed after 2005.
Consequences#
End of Free Lunch#
Before power wall:
- Just wait → faster single-thread
- Software automatically faster
After power wall:
- Must redesign software
- Parallelism required
Multi-core Era#
Instead of faster single cores:
- Multiple slower cores
- Same total power budget
- Parallel software needed
Power Management Techniques#
Dynamic Voltage and Frequency Scaling (DVFS)#
Reduce power when full performance not needed:
$$ P \propto V^2 \cdot f $$$$ f \propto V $$Therefore:
$$ P \propto V^3 $$Lowering voltage significantly reduces power.
Clock Gating#
Turn off unused circuit blocks:
$$ P_{gated} = 0 $$Dark Silicon#
Not all transistors can be active simultaneously:
$$ \text{Active area} = \frac{P_{budget}}{P_{density}} $$Some transistors must stay “dark.”
Modern Approaches#
Heterogeneous Computing#
| Core Type | Power | Performance | Use Case |
|---|---|---|---|
| Big core | High | High | Demanding tasks |
| Little core | Low | Low | Background tasks |
| GPU | Variable | High throughput | Parallel tasks |
| NPU | Efficient | AI-specialized | Machine learning |
Examples#
- ARM big.LITTLE
- Intel hybrid (P-cores + E-cores)
- Apple Silicon (efficiency + performance cores)
Voltage-Frequency Relationship#
Minimum Operating Voltage#
$$ V_{min} \propto kT/q \cdot \ln\left(\frac{I_{on}}{I_{off}}\right) $$Can’t go below thermal voltage limit.
Near-Threshold Computing#
Operating near \(V_{th}\):
- Very low power
- Slow but efficient
- Used in IoT, wearables
Energy vs Performance Trade-off#
Energy-Delay Product#
$$ EDP = E \times T = P \times T^2 $$Minimizing EDP balances energy and speed.
Race to Idle#
Sometimes better to:
- Run fast, finish quickly
- Sleep in low-power state
- Total energy may be lower
Future Directions#
| Approach | Potential |
|---|---|
| 3D stacking | Better power delivery |
| New materials | Lower leakage |
| Photonics | Lower interconnect power |
| Superconducting | Near-zero resistance |
| Quantum | Different paradigm |
Summary#
The power wall:
- Ended Dennard scaling ~2005
- Stopped clock frequency growth
- Drove multi-core revolution
- Requires parallel software
- Led to heterogeneous computing
Modern chips must balance performance and power, not just maximize speed.