Table of Contents
Overview#
Gate and data lines in LCD panels present significant electrical loads to the driver ICs. Understanding these loads is essential for proper timing and power design.
Line Structure#
Physical Layout#
Gate Line (horizontal):
══════════════════════════════════════════
│ │ │ │ │ │
◯ ◯ ◯ ◯ ◯ ◯ Pixels
│ │ │ │ │ │
══════════════════════════════════════════
Data Line (vertical):
║ ║ ║ ║ ║ ║
◯ ◯ ◯ ◯ ◯ ◯ Pixels
║ ║ ║ ║ ║ ║Gate Line Load#
Equivalent Circuit#
Gate Driver
│
═╪═ Rg ═╪═ Rg ═╪═ Rg
═╪═────────═╪═────────═╪═────→
│ │ │
═╪═ Cg ═╪═ Cg ═╪═ Cg
═╪═ ═╪═ ═╪═
│ │ │
GND GND GNDLoad Components#
| Component | Source | Value |
|---|---|---|
| Rg | Line resistance | ~10-50 Ω/cm |
| Cgs | Gate-source overlap | ~10 fF/pixel |
| Cgl | Gate-line capacitance | ~1 pF/cm |
Total Gate Load#
$$ C_{gate,total} = n_{pixels} \cdot C_{gs} + L \cdot C_{line} $$For 1920-pixel row:
$$ C_{gate} \approx 1920 \times 10\text{ fF} + 30\text{ cm} \times 1\text{ pF/cm} \approx 50\text{ pF} $$Time Constant#
$$ \tau_{gate} = R_{total} \cdot C_{total} $$RC delay affects signal propagation.
Data Line Load#
Equivalent Circuit#
Data Driver
│
═╪═ Rd
═╪═
│
═╪═ Cd (Cgs + Cds)
═╪═
│
═╪═ Rd
═╪═
│
═╪═ Cd
═╪═
│
↓ (continues down)Load Components#
| Component | Source | Value |
|---|---|---|
| Rd | Line resistance | ~5-20 Ω/cm |
| Cds | Drain-source | ~50 fF/pixel |
| Cdl | Data-line capacitance | ~1 pF/cm |
Charging Requirement#
Data line must charge to final voltage within line time:
$$ t_{line} = \frac{1}{f_{frame} \times n_{rows}} $$For 60 Hz, 1080 rows:
$$ t_{line} = \frac{1}{60 \times 1080} \approx 15.4 \text{ μs} $$RC Delay Effects#
Gate Line Delay#
Voltage
│ ┌─────────────────
│ ╱
│ ╱ Delayed rise
│ ╱
│╱______________________ time
Start τ 2τ 3τVoltage at end of line rises slower than driver output.
Compensation#
- Dual-side driving: Drive from both ends
- Lower resistance: Wider metal lines
- Higher driver voltage: Compensate for RC drop
Power Consumption#
Dynamic Power#
$$ P_{dynamic} = C \cdot V^2 \cdot f $$For gate line:
$$ P_{gate} = C_{gate} \cdot V_{gate}^2 \cdot f_{frame} $$Per-Line Power#
Example calculation:
- \(C_{gate}\) = 50 pF
- \(V_{gate}\) = 25V swing
- \(f\) = 60 Hz
Data Driver Considerations#
Output Current Requirement#
$$ I_{peak} = C_{data} \cdot \frac{dV}{dt} $$Must charge line within settling time:
$$ I = C \cdot \frac{V_{swing}}{t_{settle}} $$Slew Rate#
$$ SR = \frac{V_{swing}}{t_{rise}} $$Higher resolution requires faster drivers.
Design Trade-offs#
Line Width vs Aperture#
| Wider Lines | Narrower Lines |
|---|---|
| Lower resistance | Higher resistance |
| Faster charging | Slower charging |
| Lower aperture | Higher aperture |
Material Selection#
| Material | Resistivity | Use |
|---|---|---|
| ITO | ~100 μΩ·cm | Transparent electrodes |
| Al | ~3 μΩ·cm | Gate lines |
| Cu | ~2 μΩ·cm | High-performance |
High-Resolution Challenges#
4K and Beyond#
| Resolution | Pixels/Row | Line Time |
|---|---|---|
| FHD (1080p) | 1920 | 15.4 μs |
| 4K (2160p) | 3840 | 7.7 μs |
| 8K (4320p) | 7680 | 3.8 μs |
Higher resolution means:
- More capacitance per line
- Less time to charge
- Higher driver current needed
Solutions#
- Higher refresh rate drivers
- Lower parasitic materials
- Dual/quad driving
- Advanced TFT (faster charging)