Table of Contents

Overview
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Feedback is a fundamental concept in analog circuit design, enabling stable amplification, voltage regulation, and frequency synthesis.

Negative Feedback Principle
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Input (+) ────┐
              ├──→ [Amplifier] ──→ Output
Feedback (-) ─┘
       ↑                           |
       └───────── β ←──────────────┘

Transfer Function:

$$ A_{closed} = \frac{A_{open}}{1 + A_{open} \cdot \beta} $$

Where:

  • \(A_{open}\) = Open-loop gain
  • \(\beta\) = Feedback factor

Stability Analysis
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Oscillation Condition
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If input differences oscillate between positive and negative values based on output, the system becomes an oscillator.

Barkhausen Criteria:

$$ |A \cdot \beta| = 1 \quad \text{and} \quad \angle(A \cdot \beta) = 0° $$

Frequency Response
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Gain Degradation:

  • Parasitic capacitance attenuates high frequencies
  • Gain decreases by 20 dB/decade per pole

Stability Margins
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ParameterStable Range
Pole count< 3 poles at unity gain
Phase margin45° - 60°
Gain margin> 10 dB

Bandwidth
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  • 1st-order: -3dB at first pole
  • 2nd-order: -3dB after first pole

LDO (Low Drop-Out) Regulator
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Linear voltage regulator using negative feedback.

    VIN ──→ [Pass Transistor] ──→ VOUT
                    ↑                |
              [Error Amp]            |
                    ↑                |
              VREF ─┴───── R1 ───────┤
                           |         |
                          R2         |
                           |         |
                          GND ←──────┘

Output Voltage:

$$ V_{OUT} = V_{REF} \times \left(1 + \frac{R_1}{R_2}\right) $$

Features:

  • Stable power supply
  • Low dropout voltage
  • Feedback maintains consistent output across load variations

PLL (Phase-Locked Loop)
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Essential for high-speed I/O and clock generation.

REF ──→ [Phase Detector] ──→ [Charge Pump] ──→ [Loop Filter] ──→ [VCO] ──→ OUT
              ↑                                                      |
              └────────────────── [Divider ÷N] ←─────────────────────┘

Components
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BlockFunction
Phase DetectorCompares REF and feedback phases
Charge PumpConverts phase error to current
Loop FilterSmooths control voltage
VCOVoltage-controlled oscillator
DividerFrequency division (÷N)

Output Frequency
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$$ f_{OUT} = N \times f_{REF} $$

Note: N must be integer multiples (2^n divisions of reference).

Lock Process
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  1. Phase detector compares REF vs divided output
  2. Charge pump adjusts VCO control voltage
  3. Loop filter stabilizes control signal
  4. VCO frequency adjusts until phase lock

Design Considerations
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  1. Loop stability - Adequate phase margin
  2. Bandwidth - Trade-off: speed vs noise
  3. Settling time - Time to reach lock
  4. Jitter - Minimize for clock applications