Table of Contents

Overview
#

Feedback is a fundamental concept in analog circuit design, enabling stable amplification, precise voltage regulation, and frequency synthesis. Understanding feedback principles is essential for designing reliable electronic systems.

Basic Feedback Concept
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Feedback Loop Structure
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              ┌──────────────────────┐
              │                      │
    ─────────(+)───▶ Amplifier A ────┼────▶ Output
              ▲                      │
              │                      │
              └──── Feedback β ◀─────┘

Closed-Loop Gain
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With negative feedback:

$$ A_{CL} = \frac{A}{1 + A\beta} $$

Where:

  • \(A\): Open-loop gain
  • \(\beta\): Feedback factor
  • \(A\beta\): Loop gain

For large \(A\beta\):

$$ A_{CL} \approx \frac{1}{\beta} $$

The closed-loop gain becomes independent of the amplifier gain!

Negative vs Positive Feedback
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Negative Feedback
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Output opposes input change → System converges to stable value.

Benefits:

  • Reduced sensitivity to component variations
  • Improved linearity
  • Extended bandwidth
  • Predictable gain (\(1/\beta\))

Positive Feedback
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Output reinforces input change → System diverges or oscillates.

Applications:

  • Oscillators
  • Comparators with hysteresis
  • Latches

Condition for Oscillation (Barkhausen):

$$ |A\beta| = 1 \quad \text{and} \quad \angle A\beta = 0° \text{ or } 360° $$

Frequency Response
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Parasitic Capacitance Effect
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At high frequencies, parasitic capacitance absorbs high-frequency components:

Gain (dB)
    │
    │ ────┐
    │     │ -20 dB/decade
    │     └────┐
    │          │ -40 dB/decade
    │          └────┐
    │               │ -60 dB/decade
    └─────────────────────── Frequency (log)
         f₁    f₂    f₃
        (poles)

Gain Reduction per Pole
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Each pole contributes:

  • -20 dB/decade magnitude roll-off
  • -90° phase shift (asymptotically)
Number of PolesRoll-offPhase Shift
1-20 dB/dec-90°
2-40 dB/dec-180°
3-60 dB/dec-270°

Three-Pole Threshold
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With three poles, phase shift can reach -270°, making stability critical:

$$ \text{If } |A\beta| > 1 \text{ when phase} = -180° \rightarrow \text{Unstable} $$

Stability Analysis
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Phase Margin
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The phase margin measures stability:

$$ PM = 180° + \angle A\beta \bigg|_{|A\beta|=1} $$

Acceptable Range: 45° - 60°

|Aβ| (dB)
    │
    │  \
    │   \
    │    \  ← Unity gain (0 dB)
    │─────\────────────────────
    │      \
    │       \
    └──────────────────────── f
                ↑
           Phase Margin
           measured here

Gain Margin
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$$ GM = \frac{1}{|A\beta|} \bigg|_{\angle A\beta = -180°} $$

Expressed in dB:

$$ GM_{dB} = -20\log|A\beta| \bigg|_{\angle A\beta = -180°} $$

Acceptable Range: > 10 dB

Bandwidth
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Measured at -3 dB points:

$$ BW = f_{-3dB} $$

For first-order systems:

$$ f_{-3dB} = \frac{1}{2\pi RC} $$

Applications
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LDO (Low Drop-out) Regulator
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Provides stable voltage output with minimal dropout voltage.

        VIN
         │
      ┌──┴──┐
      │Pass │
      │Trans│
      └──┬──┘
         │
         ├──────────── VOUT
         │
        ┌┴┐
        │R1│
        └┬┘
         │
         ├───▶ Error Amp ◀─── VREF
         │
        ┌┴┐
        │R2│
        └┬┘
         │
        GND

Output Voltage:

$$ V_{OUT} = V_{REF}\left(1 + \frac{R_1}{R_2}\right) $$

Key Specifications:

  • Dropout voltage: \(V_{IN} - V_{OUT,min}\)
  • Line regulation: \(\Delta V_{OUT}/\Delta V_{IN}\)
  • Load regulation: \(\Delta V_{OUT}/\Delta I_{LOAD}\)
  • PSRR: Power supply rejection ratio

PLL (Phase-Locked Loop)
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Maintains constant output frequency locked to a reference.

    ┌─────────────────────────────────────────┐
    │                                         │
    │    ┌───────┐   ┌──────┐   ┌─────┐      │
FREF──▶│Phase  │──▶│Charge│──▶│Loop │──▶VCO──┼──▶FOUT
    │   │Detect │   │Pump  │   │Filter│      │
    │   └───────┘   └──────┘   └─────┘      │
    │       ▲                                │
    │       │       ┌────────┐               │
    │       └───────│Divider │◀──────────────┘
    │               │  ÷N    │
    │               └────────┘
    └─────────────────────────────────────────┘

Locked Condition:

$$ F_{OUT} = N \cdot F_{REF} $$

Components:

BlockFunction
Phase DetectorCompares phases of FREF and divided output
Charge PumpConverts phase error to current
Loop FilterSmooths control voltage
VCOVoltage-controlled oscillator
DividerDivides output frequency by N

Frequency Adjustment:

$$ N = 2^n \quad \text{for integer-N PLLs} $$

Fractional-N PLLs allow finer frequency steps.

Design Guidelines
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Compensation Techniques
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IssueSolution
Low phase marginDominant pole compensation
Slow responseIncrease bandwidth
PeakingReduce Q factor
OscillationAdd compensation capacitor

Dominant Pole Compensation
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Add a low-frequency pole to ensure stability:

$$ f_d \ll f_1, f_2, f_3 $$

This ensures 20 dB/decade roll-off at unity gain.

Summary
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Key concepts in feedback systems:

  1. Negative feedback: Stabilizes gain to \(1/\beta\)
  2. Phase margin: 45°-60° for stability
  3. Poles: Each adds -90° phase shift
  4. Three poles: Critical stability threshold
  5. LDO: Voltage regulation via feedback
  6. PLL: Frequency synthesis via phase feedback