Table of Contents

Overview
#

Digital gate design requires careful consideration of transistor sizing, capacitance effects, and timing optimization. This guide covers the fundamental principles of CMOS logic gate design.

NMOS vs PMOS Mobility
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The Mobility Problem
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NMOS transistors have approximately 2× higher mobility than PMOS:

$$ \mu_n \approx 2\mu_p $$

This means for the same dimensions, NMOS can carry more current:

$$ I_D = \frac{1}{2}\mu C_{ox}\frac{W}{L}(V_{GS} - V_{th})^2 $$

Solution: Width Compensation
#

To achieve equal rise and fall times, PMOS width is doubled:

$$ W_p = 2W_n $$

Symmetric Inverter:

        VDD
         │
      ┌──┴──┐
      │ PMOS│  W = 2W_n
      └──┬──┘
         │
In ──────┼────── Out
         │
      ┌──┴──┐
      │ NMOS│  W = W_n
      └──┬──┘
         │
        GND

Result:

  • \(t_{rise} \approx t_{fall}\)
  • Consistent switching behavior
  • Predictable timing

Oxide Capacitance
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Definition
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Gate oxide capacitance per unit area:

$$ C_{ox} = \frac{\varepsilon_{ox}}{t_{ox}} $$

Where:

  • \(\varepsilon_{ox}\): Oxide permittivity (\(\approx 3.9\varepsilon_0\) for SiO₂)
  • \(t_{ox}\): Oxide thickness

Impact on Performance
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Larger \(C_{ox}\):

  • Better gate control over channel
  • Higher drive current
  • Improved \(g_m\)

Trade-off:

  • Increased gate capacitance
  • Higher leakage current (thin oxide)

Scaling Trends#

Technology\(t_{ox}\) (nm)\(C_{ox}\) (fF/μm²)
180nm4.08.6
90nm2.017.2
45nm1.228.7
22nm0.938.3

Depletion Capacitance Modulation
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Body Effect Factor
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The factor \(m\) captures short-channel effects:

$$ m = 1 + \frac{C_{dm}}{C_{ox}} $$

Where \(C_{dm}\) is the depletion capacitance modulation.

Interpretation:

  • \(m \approx 1\): Long channel behavior
  • \(m > 1\): Short channel effects present
  • Higher \(m\) indicates stronger substrate influence

Impact on Threshold Voltage
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$$ V_{th} = V_{th,long} - \Delta V_{th} $$

Short-channel effects reduce threshold voltage.

Series Transistor Sizing
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NMOS in Series
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For NAND gates, series NMOS requires width increase:

        Out
         │
      ┌──┴──┐
 A ───│NMOS1│  W = 2W_n
      └──┬──┘
         │
      ┌──┴──┐
 B ───│NMOS2│  W = 2W_n
      └──┬──┘
         │
        GND

Reasoning:

  • Series resistance doubles
  • Double width to maintain current

PMOS in Series
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For NOR gates, series PMOS needs 4× width:

        VDD
         │
      ┌──┴──┐
 A ───│PMOS1│  W = 4W_n
      └──┬──┘
         │
      ┌──┴──┐
 B ───│PMOS2│  W = 4W_n
      └──┬──┘
         │
        Out

Calculation:

  • Base PMOS: 2× (mobility compensation)
  • Series: 2× (resistance compensation)
  • Total: 2 × 2 = 4×

General Sizing Rule
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For \(n\) transistors in series:

$$ W_{series} = n \times W_{single} $$

Gate Delay Optimization
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Propagation Delay
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$$ t_p = \frac{C_L \cdot V_{DD}}{2 \cdot I_{avg}} $$

Where:

  • \(C_L\): Load capacitance
  • \(V_{DD}\): Supply voltage
  • \(I_{avg}\): Average switching current

Tapered Buffer Chain
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For driving large capacitive loads, use progressively sized buffers:

                 ┌───┐    ┌───┐    ┌───┐
In ──▶│ 1 │──▶│ f │──▶│f² │──▶ Out
                 └───┘    └───┘    └───┘
                  W        fW       f²W

Optimal Tapering Factor:

$$ f_{opt} = e \approx 2.7 $$

Number of Stages:

$$ N = \log_f\left(\frac{C_{out}}{C_{in}}\right) $$

Minimum Delay:

$$ t_{total} = N \cdot t_{unit} \cdot f $$

Comparison: Single Buffer vs. Tapered Chain
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ApproachDelayArea
Single large bufferHigh (large input cap)Large
Tapered chainLower (distributed)Similar total

Logic Gate Sizing
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NAND Gate
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        VDD
         │
      ┌──┴──┐   ┌──┴──┐
 A ───│ Pp  │───│ Pp  │─── B
      └──┬──┘   └──┬──┘
         └────┬────┘
              │
             Out
              │
           ┌──┴──┐
      A ───│ 2Wn │
           └──┬──┘
           ┌──┴──┐
      B ───│ 2Wn │
           └──┬──┘
              │
             GND

Sizing:

  • PMOS: \(W_p\) (parallel, no increase needed)
  • NMOS: \(2W_n\) (series, doubled)

NOR Gate
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        VDD
         │
      ┌──┴──┐
 A ───│ 4Wp │
      └──┬──┘
      ┌──┴──┐
 B ───│ 4Wp │
      └──┬──┘
         │
        Out
         │
      ┌──┴──┐   ┌──┴──┐
 A ───│ Wn  │───│ Wn  │─── B
      └──┬──┘   └──┬──┘
         └────┬────┘
             GND

Sizing:

  • PMOS: \(4W_p\) (series, ×2 for mobility, ×2 for series)
  • NMOS: \(W_n\) (parallel, no increase)

Capacitance Components
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Total Gate Capacitance
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$$ C_{total} = C_g + C_{gd,overlap} + C_{gs,overlap} $$

Where:

  • \(C_g = C_{ox} \cdot W \cdot L\): Gate capacitance
  • \(C_{gd,overlap}\): Gate-drain overlap
  • \(C_{gs,overlap}\): Gate-source overlap

Load Capacitance
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$$ C_L = C_{self} + C_{wire} + C_{fanout} $$

Summary
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Key principles in digital gate design:

  1. PMOS sizing: 2× NMOS width for equal mobility
  2. Series transistors: Multiply width by series count
  3. Tapered buffers: Optimal factor \(f \approx e\)
  4. NAND: Efficient (NMOS in series smaller area)
  5. NOR: Less efficient (PMOS in series requires large area)
  6. Trade-offs: Speed vs. area vs. power