Digital Circuits

Overview

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Digital circuits form the foundation of modern computing, from simple logic gates to complex processors and memory systems.

Hierarchical Design Structure

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Physical Layer (Silicon)
    ↓
Transistor Level (NMOS/PMOS)
    ↓
Logic Gates (AND, OR, NOT)
    ↓
Functional Blocks (ALU, Registers)
    ↓
Processor / Memory Architecture

Programming Languages

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Transistor Basics

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NMOS and PMOS

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In digital circuits, transistors function as discrete switches, not amplifiers.

CMOS Inverter

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        VDD
         |
       [PMOS]
         |
Input ---+--- Output
         |
       [NMOS]
         |
        GND

RTL Design Process

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RTL = Register Transfer Level

1. Behavioral Description - High-level functionality
2. Synthesis - Convert to gate-level
3. Placement & Routing - Physical layout
4. Timing Analysis - Verify timing constraints

Verilog Basics

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Module Definition

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module my_module (
    input  wire clk,
    input  wire reset,
    input  wire [7:0] data_in,
    output reg  [7:0] data_out
);
    // Module logic here
endmodule

Port Connections

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Positional:

my_module inst1 (clk, reset, din, dout);

Named (Recommended):

my_module inst1 (
    .clk(system_clk),
    .reset(sys_reset),
    .data_in(input_data),
    .data_out(output_data)
);

Blocking vs Non-Blocking

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Combinational Logic:

always @(*) begin
    y = a & b;      // Blocking
    z = y | c;      // Executes after y
end

Sequential Logic:

always @(posedge clk) begin
    q <= d;         // Non-blocking
    q2 <= q;        // Both execute simultaneously
end

Timing Concepts

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Propagation Delay

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Time for signal to travel through a gate:

• Rise time (t_r)
• Fall time (t_f)
• Propagation delay (t_pd)

Clock Skew

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Problem: Clock arrives at different times due to:

• Wire length differences
• External noise
• Temperature variations

Solution: Phase-Locked Loop (PLL)

• Synchronizes clock distribution
• Compensates for skew
• Generates clean clock edges

Design Tips

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1. Use non-blocking for flip-flops - Prevents race conditions
2. Synchronize inputs - Use double-flip-flop for async signals
3. Reset all registers - Ensure known initial state
4. Avoid latches - Use complete if-else or case statements