Table of Contents

Overview
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CPU design involves creating the hardware that fetches, decodes, and executes instructions. This post covers fundamental concepts in processor datapath design.

CPU Components
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Datapath Elements
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┌─────────────────────────────────────────────────────────┐
│                        CPU                               │
│  ┌──────┐   ┌────┐   ┌─────┐   ┌─────┐   ┌──────┐      │
│  │  PC  │──→│I-Mem│──→│ Regs│──→│ ALU │──→│D-Mem │      │
│  └──────┘   └────┘   └─────┘   └─────┘   └──────┘      │
│      ↑                  ↑          ↓         ↓          │
│      └──────────────────┴──────────┴─────────┘          │
└─────────────────────────────────────────────────────────┘

Key Components
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ComponentFunction
PCProgram Counter - holds current instruction address
I-MemInstruction Memory
RegistersFast storage (32 registers typical)
ALUArithmetic Logic Unit
D-MemData Memory

Single-Cycle Datapath
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Instruction Fetch
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PC ──→ [I-Mem] ──→ Instruction
 ↑
PC + 4

R-Type Execution
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Instruction
    ↓
[Decode: rs1, rs2, rd]
    ↓
[Read Registers]
    ↓
[ALU Operation]
    ↓
[Write to rd]

Load Instruction
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Instruction
    ↓
[Decode: rs1, imm, rd]
    ↓
[Read rs1] + imm ──→ Address
    ↓
[Read D-Mem at Address]
    ↓
[Write to rd]

Control Signals
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ALU Control
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ALU OpFunction
0000AND
0001OR
0010ADD
0110SUB
0111SLT

Main Control
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SignalMeaning
RegWriteWrite to register file
MemReadRead from data memory
MemWriteWrite to data memory
BranchConditional branch
ALUSrcALU second operand source

Pipelined Datapath
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Five-Stage Pipeline
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IF → ID → EX → MEM → WB
│    │    │     │     │
↓    ↓    ↓     ↓     ↓
Fetch Decode Execute Memory Writeback

Pipeline Registers
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       IF/ID    ID/EX    EX/MEM   MEM/WB
         │        │        │        │
[IF] ──→ ║ ──→ [ID] ──→ ║ ──→ [EX] ──→ ║ ──→ [MEM] ──→ ║ ──→ [WB]

Hazard Handling
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Data Hazards
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Forwarding (Bypassing):

ADD R1, R2, R3   ; R1 = R2 + R3
SUB R4, R1, R5   ; R1 needed immediately
                   ↑
            Forward from EX/MEM

Stalling:

When forwarding isn’t possible (load-use):

LW  R1, 0(R2)    ; Load R1
ADD R3, R1, R4   ; Need R1 - must stall

Insert bubble (NOP) for one cycle.

Control Hazards
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Branch Prediction:

StrategyDescription
StaticAlways/never taken
DynamicBased on history
BTBBranch Target Buffer
$$ \text{CPI}_{branch} = 1 + p_{wrong} \times \text{penalty} $$

Performance Analysis
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CPI Calculation
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$$ \text{CPI} = 1 + \text{stall cycles per instruction} $$

Pipeline Speedup
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Ideal speedup = number of stages

$$ \text{Speedup} = \frac{n}{1 + \text{stall rate} \times \text{stall cycles}} $$

Advanced Techniques
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Superscalar
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Execute multiple instructions per cycle:

Cycle 1: [IF IF] [ID ID] [EX EX] [MEM MEM] [WB WB]

Issue width = 2, 4, or more.

Out-of-Order Execution
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  1. Fetch in order
  2. Decode and rename registers
  3. Execute when operands ready (out of order)
  4. Commit in order

Branch Prediction
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$$ \text{Accuracy} = \frac{\text{Correct predictions}}{\text{Total branches}} $$

Modern predictors achieve >95% accuracy.

Design Trade-offs
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ApproachProsCons
Single-cycleSimpleLong cycle time
Multi-cycleShorter cycleComplex control
PipelinedHigh throughputHazards
SuperscalarHigher IPCComplex, power hungry

Critical Path
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The longest path determines cycle time:

$$ T_{cycle} = \max(\text{all paths through combinational logic}) $$

Common critical paths:

  • Memory access
  • ALU operations
  • Register file access